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| FEATURES LTC3810-5 60V Current Mode Synchronous Switching Regulator Controller DESCRIPTIO The LTC(R)3810-5 is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 60V, making it ideal for telecom and automotive applications. The LTC3810-5 uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifier provides very fast line and load transient response. Large 1 gate drivers allow the LTC3810-5 to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. A shutdown pin allows the LTC3810-5 to be turned off, reducing the supply current to 240A. Integrated bias control generates gate drive power from the input supply during start-up or when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher efficiency. High Voltage Operation: Up to 60V Large 1 Gate Drivers No Current Sense Resistor Required Dual N-Channel MOSFET Synchronous Drive Extremely Fast Transient Response 0.5% 0.8V Voltage Reference Programmable Output Voltage Tracking/Soft-Start Generates 5.5V Driver Supply from Input Supply Synchronizable to External Clock Selectable Pulse Skip Mode Operation Power Good Output Voltage Monitor Adjustable On-Time/Frequency: tON(MIN) < 100ns Adjustable Cycle-by-Cycle Current Limit Programmable Undervoltage Lockout Output Overvoltage Protection Thermally Enhanced 32-Pin QFN Package APPLICATIO S 48V Telecom and Base Station Power Supplies Networking Equipment, Servers Automotive and Industrial Control Systems , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611. TYPICAL APPLICATIO 274k ION PGOOD VRNG 1000pF NDRV BOOST TG 0.1F SW EXTVCC DRVCC SHDN ITH 200k VFB 47pF SGND INTVCC SENSE+ BG SENSE- BGRTN 100k High Efficiency High Voltage Step-Down Converter + ZXMN10A07F VIN 13V TO 60V 22F EFFICIENCY (%) LTC3810-5 Si7450DP 10F VOUT 12V/6A 14k MODE/SYNC SS/TRACK + MBR1100 Si7450DP 270F 5pF 1F 1k 38105 TA01 U U U Efficiency vs Load Current 100 VIN = 24V 95 VIN = 42V 90 85 0 1 2 3 4 LOAD CURRENT (A) 5 6 38105 TA01b 38105f 1 LTC3810-5 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW BOOST SW ION NC NC NC NC TG Supply Voltages INTVCC, DRVCC ...................................... -0.3V to 14V (DRVCC - BGRTN), (BOOST - SW) ......... -0.3V to 14V BOOST (Continuous) ............................. -0.3V to 85V BOOST (400ms) .................................. -0.3V to 95V BGRTN ........................................................ -5V to 0V EXTVCC .................................................. -0.3V to 15V (EXTVCC - INTVCC) ................................. -14V to 12V (NDRV - INTVCC) Voltage ........................... -0.3V to 10V SW, SENSE+ Voltage (Continuous) ............... -1V to 70V SW, SENSE+ Voltage (400ms) ...................... -1V to 80V ION Voltage (Continuous) ........................... -0.3V to 70V ION Voltage (400ms) .................................. -0.3V to 80V SS/TRACK Voltage ....................................... -0.3V to 5V PGOOD Voltage ............................................ -0.3V to 7V VRNG, VON, MODE/SYNC, SHDN, UVIN Voltages........................................ -0.3V to 14V PLL/LPF, FB Voltages ................................ -0.3V to 2.7V TG, BG, INTVCC, EXTVCC RMS Currents .................50mA Operating Temperature Range (Note 2) ... -40C to 85C Junction Temperature (Notes 3, 7) ....................... 125C Storage Temperature Range................... -65C to 125C 32 31 30 29 28 27 26 25 NC 1 VON 2 VRNG 3 PGOOD 4 MODE/SYNC 5 ITH 6 VFB 7 PLL/LPF 8 9 10 11 12 13 14 15 16 SS/TRACK EXTVCC INTVCC NC NC SHDN UVIN NDRV 33 24 SENSE+ 23 NC 22 NC 21 NC 20 SENSE- 19 BGRTN 18 BG 17 DRVCC UH PACKAGE 32-LEAD (5mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC3810EUH-5 UH PART MARKING 38105 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges or for other package options. ELECTRICAL CHARACTERISTICS SYMBOL Main Control Loop INTVCC IQ IBOOST VFB INTVCC Supply Voltage INTVCC Supply Current INTVCC Shutdown Current BOOST Supply Current Feedback Voltage PARAMETER The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN = VEXTVCC = VNDRV = 5V, VMODE/SYNC = VSENSE+ = VSENSE - = VBGRTN = VSW = 0V, unless otherwise specified. CONDITIONS MIN 4.35 TYP MAX 14 UNITS V mA A A A V V V %/V SHDN > 1.5V (Note 5) SHDN = 0V (Note 5) SHDN = 0V (Note 4) 0C to 85C -40C to 85C 5V < INTVCC < 14V (Note 4) 3 240 270 0 0.796 0.794 0.792 0.800 0.800 0.800 0.002 6 600 400 5 0.804 0.806 0.806 0.02 VFB,LINE Feedback Voltage Line Regulation 38105f 2 U W U U WW W LTC3810-5 The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN = VEXTVCC = VNDRV = 5V, VMODE/SYNC = VSENSE+ = VSENSE - = VBGRTN = VSW = 0V, unless otherwise specified. SYMBOL VSENSE(MAX) PARAMETER Maximum Current Sense Threshold CONDITIONS VRNG = 2V, VFB = 0.76V VRNG = 0V, VFB = 0.76V VRNG = INTVCC, VFB = 0.76V VRNG = 2V, VFB = 0.84V VRNG = 0V, VFB = 0.84V VRNG = INTVCC, VFB = 0.84V 65 MIN 256 70 170 TYP 320 95 215 -300 -85 -200 20 100 25 0.75 1.2 VSHDN = 5V UVIN Rising UVIN Falling Hysteresis INTVCC Rising, INDRV = 100A INTVCC Rising, NDRV = INTVCC = EXTVCC INTVCC Rising, NDRV = INTVCC, EXTVCC = 0 INTVCC Falling ION = 100A ION = 300A ION = 2000A 250 ION = 100A, VPLL/LPF = 2V ION = 100A, VPLL/LPF = 0.5V fPLLIN < fOSC fPLLIN > fOSC VBG = 0V VTG - VSW = 0 0.7 0.7 2.2 0.6 3.6 1.2 15 -25 1 1 1 1 VFB Rising, VUVOV = 0V VFB Falling, VUVOV = 0V VFB Returning IPGOOD = 5mA VPGOOD = 5V VFB Falling 7.5 -7.5 10 -10 1.5 0.3 0 120 1.5 12.5 -12.5 3 0.6 2 1.5 ELECTRICAL CHARACTERISTICS MAX 384 120 260 UNITS mV mV mV mV mV mV VSENSE(MIN) Minimum Current Sense Threshold IVFB AVOL(EA) fU VMODE/SYNC IMODE/SYNC VSHDN ISHDN VUVIN Feedback Current Error Amplifier DC Open Loop Gain Error Amp Unity Gain Crossover Frequency MODE/SYNC Threshold MODE/SYNC Current Shutdown Threshold SHDN Pin Input Current UVIN Undervoltage Lockout 150 nA dB MHz 0.8 0 1.5 0 0.89 0.80 0.10 4.2 4.2 9 4.0 1.85 605 0.85 1 2 1 0.92 0.82 0.12 4.35 4.35 9.30 4.15 2.15 695 100 350 5 1.8 V A V A V V V V V V V s ns ns ns s s A A A A % % % V A s 38105f 0.86 0.78 0.07 4.05 4.05 8.70 3.85 1.55 515 VVCCUV INTVCC Undervoltage Lockout Linear Regulator Mode External Supply Mode Trickle-Charge Mode Oscillator and Phase-Locked Loop tON tON(MIN) tOFF(MIN) tON(PLL) On-Time Minimum On-Time Minimum Off-Time tON Modulation Range by PLL Up Modulation Down Modulation Phase Detector Output Current Sinking Capability Sourcing Capability BG Driver Peak Source Current BG Driver Pull-Down RDS(ON) TG Driver Peak Source Current TG Driver Pull-Down RDS(ON) PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysterisis PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay IPLLFLTR Driver IBG,PEAK RBG,SINK ITG,PEAK RTG,SINK PGOOD Output VFBOV VFB,HYST VPGOOD IPGOOD PG Delay 3 LTC3810-5 The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN = VEXTVCC = VNDRV = 5V, VMODE/SYNC = VSENSE+ = VSENSE- = VBGRTN = VSW = 0V, unless otherwise specified. SYMBOL Tracking ISS/TRACK VFB,TRACK VCC Regulators VEXTVCC EXTVCC Switchover Voltage EXTVCC Rising EXTVCC Hysterisis INTVCC Voltage from EXTVCC VEXTVCC - VINTVCC at Dropout INTVCC Load Regulation from EXTVCC INTVCC Voltage from NDRV Regulator INTVCC Load Regulation from NDRV Current into NDRV Pin Linear Regulator Timeout Enable Threshold Maximum Supply Voltage Maximum Current into NDRV/INTVCC Trickle Charger Shunt Regulator Trickle Charger Shunt Regulator, INTVCC 16.7V (Note 9) 10 6V < VEXTVCC < 15V ICC = 20mA, VEXTVCC = 5V ICC = 0mA to 20mA, VEXTVCC = 10V Linear Regulator in Operation ICC = 0mA to 20mA, VEXTVCC = 0 Linear Regulator in Operation 20 210 5.2 ELECTRICAL CHARACTERISTICS PARAMETER SS/TRACK Source Current Feedback Voltage at Tracking CONDITIONS VSS/TRACK > 0.3V VTRACK = 0V, ITH = 1.2V (Note 4) VTRACK = 0.5V, ITH = 1.2V (Note 4) MIN 0.7 0.48 TYP 1.4 -0.018 0.5 MAX 2.5 0.52 UNITS A V V 4.45 0.1 5.2 4.7 0.25 5.5 75 0.01 5.5 0.01 40 270 15 0.4 5.8 150 5.8 60 350 V V V mV % V % A A V mA VINTVCC,1 VEXTVCC,1 VLOADREG,1 VINTVCC,2 VLOADREG,2 INDRV INDRVTO VCCSR ICCSR Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3810E-5 is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3810-5: TJ = TA + (PD * 34C/W) Note 4: The LTC3810-5 is tested in a feedback loop that servos VFB to the reference voltage with the ITH pin forced to a voltage between 1V and 2V. PARAMETER Maximum VIN MOSFET Gate Drive INTVCC INTVCC UV+ UV- LTC3810 100V 6.35V to 14V 6.2V 6V Note 5: The dynamic input supply current is higher due to the power MOSFET gate charging being delivered at the switching frequency (QG * fOSC). Note 6: Guaranteed by design. Not subject to test. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8: RDS(ON) guaranteed by correlation to wafer level measurement. Note 9: ICC is the sum of current into NDRV and INTVCC. LTC3810-5 60V 4.5V to 14V 4.2V 4V LTC3812-5 60V 4.5V to 14V 4.2V 4V 38105f 4 LTC3810-5 TYPICAL PERFOR A CE CHARACTERISTICS Load Transient Response VOUT 100mV/DIV INTVCC 5V/DIV VOUT 5V/DIV VIN 50V/DIV IL 5A/DIV 50s/DIV FRONT PAGE CIRCUIT VIN = 48V 0A TO 5A LOADSTEP 38105 G01 IOUT 5A/DIV Short-Circuit/ Foldback Operation VOUT 5V/DIV VFB 0.5V/DIV IL 5A/DIV 200s/DIV FRONT PAGE CIRCUIT VIN = 48V 38105 G04 Efficiency vs Input Voltage 100 IOUT = 5A 95 90 IOUT = 0.5A 90 85 80 75 70 70 80 100 FREQUENCY (kHz) EFFICIENCY (%) EFFICIENCY (%) 80 VOUT = 12V Si7852 MOSFETs f = 250kHz 10 20 50 40 30 60 INPUT VOLTAGE (V) 70 UW Start-Up VOUT 10V/DIV SS/TRACK 4V/DIV IL 5A/DIV 38105 G02 Short Circuit/ Fault Timeout Operation INTVCC 500s/DIV FRONT PAGE CIRCUIT VIN = 48V ILOAD = 1A MODE/SYNC = 0V 10ms/DIV FRONT PAGE CIRCUIT VIN = 48V RSHORT = 0.1 38105 G03 Tracking VOUT 5V/DIV SS/TRACK 0.5V/DIV VFB 0.5V/DIV IL 5A/DIV 500s/DIV FRONT PAGE CIRCUIT VIN = 48V ILOAD = 1A MODE/SYNC = 0V VOUT SS/TRACK 100mV/DIV VFB ITH 0.5V/DIV IL 2A/DIV 38105 G05 Pulse Skip Mode Operation 20s/DIV FRONT PAGE CIRCUIT VIN = 48V IOUT = 100mA MODE/SYNC = INTVCC 38105 G06 Efficiency vs Load Current 280 VIN = 12V VIN = 36V VIN = 60V 270 Frequency vs Input Voltage 260 IOUT = 0A 250 IOUT = 5A VOUT = 5V Si7850 MOSFETs MODE/SYNC = INTVCC f = 250kHz 0 1 5 2 3 4 LOAD CURRENT (A) 6 7 240 FRONT PAGE CIRCUIT MODE/SYNC = 0V 10 20 50 40 30 60 INPUT VOLTAGE (V) 70 80 230 38105 G07 38105 G08 38105 G09 38105f 5 LTC3810-5 TYPICAL PERFOR A CE CHARACTERISTICS Frequency vs Load Current 350 300 FREQUENCY (kHz) 250 200 150 PULSE SKIP 100 50 0 0 1 2 3 4 5 38105 G10 FORCED CONTINUOUS CURRENT SENSE THRESHOLD (mV) 100 0 -100 -200 -300 -400 ON-TIME (ns) LOAD CURRENT (A) On-Time vs VON Voltage 700 600 500 ON-TIME (ns) ON-TIME (ns) 400 300 200 100 0 0 0.5 2 1.5 1 VON VOLTAGE (V) ION = 300A 2.5 3 38105 G13 660 640 620 600 580 560 -50 -25 ION = 300A 50 25 75 0 TEMPERATURE (C) 100 125 MAXIMUM CURRENT SENSE THRESHOLD (mV) Maximum Current Sense Threshold vs VRNG Voltage MAXIMUM CURRENT SENSE THRESHOLD (mV) MAXIMUM CURRENT SENSE THRESHOLD (mV) 400 230 300 REFERENCE VOLTAGE (V) 200 100 0 0.5 1 1.5 VRNG VOLTAGE (V) 38105 G16 6 UW Current Sense Threshold vs ITH Voltage 400 300 200 1.4V 1V 0.7V 0.5V 1000 10000 VRNG = 2V On-Time vs ION Current VON = INTVCC 100 10 0 0.5 1.0 2.0 1.5 ITH VOLTAGE (V) 2.5 3.0 10 100 1000 ION CURRENT (A) 10000 38105 G12 38105 G11 On-Time vs Temperature 680 250 Current Limit Foldback 200 150 100 50 VRNG = INTVCC 0 0.2 0.4 VFB (V) 0.6 0.8 38105 G15 0 38105 G14 Maximum Current Sense Threshold vs Temperature 0.803 0.802 0.801 0.800 0.799 0.798 VRNG = INTVCC 50 25 0 75 TEMPERATURE (C) 100 125 Reference Voltage vs Temperature 220 210 200 190 2 180 -50 -25 0.797 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125 38105 G17 38105 G18 38105f LTC3810-5 TYPICAL PERFOR A CE CHARACTERISTICS Driver Peak Source Current vs Temperature 1.5 1.75 VBOOST = VINTVCC = 5V 1.50 1.25 RDS(ON) () 1.0 1.00 0.75 0.50 0.5 -50 0.25 -50 -25 PEAK SOURCE CURRENT (A) PEAK SOURCE CURRENT (A) 50 25 75 0 TEMPERATURE (C) 100 125 -25 75 0 25 50 TEMPERATURE (C) Driver Pulldown RDS(ON) vs Supply Voltage 1.1 7 6 1.0 RESISTANCE () 5 4 3 2 0.7 1 0.9 INTVCC CURRENT (mA) RDS(ON) () 0.8 0.6 4 5 6 7 8 9 10 11 12 13 14 DRVCC/BOOST VOLTAGE (V) 38105 G22 INTVCC Shutdown Current vs Temperature 400 INTVCC = 5V 3.5 3.0 INTVCC CURRENT (A) INTVCC CURRENT (A) 300 2.5 2.0 1.5 1.0 0.5 0 -50 -25 0 0 50 75 25 TEMPERATURE (C) 100 125 200 100 UW 100 Driver Pulldown RDS(ON) vs Temperature VBOOST = VINTVCC = 5V 3.0 2.5 2.0 1.5 1.0 0.5 0 Driver Peak Source Current vs Supply Voltage 125 4 5 6 7 8 9 10 11 12 13 14 DRVCC/BOOST VOLTAGE (V) 38105 G21 38105 G19 38105 G20 EXTVCC LDO Resistance at Dropout vs Temperature 4 INTVCC Current vs Temperature 3 2 1 0 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 38105 G23 38105 G24 INTVCC Current vs INTVCC Voltage 0 2 8 6 10 4 INTVCC VOLTAGE (V) 12 14 38105 G25 38105 G26 38105f 7 LTC3810-5 TYPICAL PERFOR A CE CHARACTERISTICS INTVCC Shutdown Current vs INTVCC Voltage 300 250 200 150 100 50 0 0 2 8 6 10 4 INTVCC VOLTAGE (V) 12 14 0 -50 -25 SS/TRACK CURRENT (A) INTVCC CURRENT (A) 2 3 ITH Voltage vs Load Current 2.5 2.2 2.0 SHUTDOWN THRESHOLD (V) 2.0 ITH VOLTAGE (V) 1.8 1.6 1.4 1.2 1.0 0.8 0 0 1 FRONT PAGE CIRCUIT 4 3 5 2 LOAD CURRENT (A) 6 7 1.5 1.0 0.5 8 UW SS/TRACK Pull-Up Current vs Temperature 1 50 25 75 0 TEMPERATURE (C) 100 125 38105 G27 38105 G28 Shutdown Threshold vs Temperature 0.6 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 38105 G29 38105 G30 38105f LTC3810-5 PIN FUNCTIONS VON (Pin 2): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage or to an external resistive divider from the output makes the on-time proportional to VOUT. The comparator defaults to 0.7V when the pin is grounded and defaults to 2.4V when the pin is connected to INTVCC. Tie this pin to INTVCC in high VOUT applications to use a lower RON value. VRNG (Pin 3): Sense Voltage Limit Set. The voltage at this pin sets the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The nominal sense voltage defaults to 95mV when this pin is tied to ground, and 215mV when tied to INTVCC. PGOOD (Pin 4): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not between 10% of the regulation point. The output voltage must be out of regulation for at least 120s before the power good output is pulled to ground. MODE/SYNC (Pin 5): Pulse skip Mode Enable/Sync Pin. This multifunction pin provides pulse skip mode enable/ disable control and an external clock input to the phase detector. Pulling this pin below 0.8V or to an external logic-level synchronization signal disables pulse skip mode operation and forces continuous operation. Pulling this pin above 0.8V enables pulse skip mode operation. For a clock input, the phase-locked loop will force the rising top gate signal to be synchronized with the rising edge of the clock signal.This pin can also be connected to a feedback resistor divider from a secondary winding on the inductor to regulate a second output voltage. ITH (Pin 6): Error Amplifier Compensation Point and Current Control Threshold. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 1.2V corresponding to zero sense voltage (zero current). VFB (Pin 7): Feedback Input. Connect VFB through a resistor divider network to VOUT to set the output voltage. PLL/LPF (Pin 8): The phase-locked loop's lowpass filter is tied to this pin. The voltage at this pin defaults to 1.2V when the IC is not synchronized with an external clock at the MODE/SYNC pin. SS/TRACK (Pin 9): Soft-Start/Tracking Input. For soft-start, a capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 0.6 s/F). For coincident or ratiometric tracking, connect this pin to a resistive divider between the voltage to be tracked and ground. SHDN (Pin 12): Shutdown Pin. Pulling this pin below 1.5V will shut down the LTC3810-5, turn off both of the external MOSFET switches and reduce the quiescent supply current to 240A. UVIN (Pin 13): UVLO Input. This pin is input to the internal UVLO and is compared to an internal 0.8V reference. An external resistor divider is connected to this pin and the input supply to program the undervoltage lockout voltage. When UVIN is less than 0.8V, the LTC3810-5 is shut down. NDRV (Pin 14): Drive Output for External Pass Device of the Linear Regulator for INTVCC. Connect to the gate of an external NMOS pass device and a pull-up resistor to the input voltage VIN. EXTVCC (Pin 15): External Driver Supply Voltage. When this voltage exceeds 4.7V, an internal switch connects this pin to INTVCC through an LDO and turns off the exter-nal MOSFET connected to NDRV, so that controller and gate drive are drawn from EXTVCC. INTVCC (Pin 16): Main Supply Pin. All internal circuits except the output drivers are powered from this pin. INTVCC should be bypassed to ground (Pin 10) with at least a 0.1F capacitor in close proximity to the LTC3810-5. DRVCC (Pin 17): Driver Supply Pin. DRVCC supplies power to the BG output driver. This pin is normally connected to INTVCC. DRVCC should be bypassed to BGRTN (Pin 20) with a low ESR (X5R or better) 1F-10F capacitor in close proximity to the LTC3810-5. 38105f 9 LTC3810-5 PIN FUNCTIONS BG (Pin 18): Bottom Gate Drive. The BG pin drives the gate of the bottom N-channel synchronous switch MOSFET. This pin swings from BGRTN to DRVCC. BGRTN (Pin 19): Bottom Gate Return. This pin connects to the source of the pulldown MOSFET in the BG driver and is normally connected to ground. Connecting a negative supply to this pin allows the synchronous MOSFET's gate to be pulled below ground to help prevent false turn-on during high dV/dt transitions on the SW node. See the Applications Information section for more details. SENSE+, SENSE- (Pin 20, Pin 24): Current Sense Comparator Input. The (+) input to the current comparator is normally connected to SW unless using a sense resistor. The (-) input is used to accurately kelvin sense the bottom side of the sense resistor or MOSFET. SW (Pin 25): Switch Node Connection to Inductor and Bootstrap Capacitor. The voltage swing at this pin is -0.7V (a Schottky diode (external) voltage drop) to VIN. TG (Pin 26): Top Gate Drive. The TG pin drives the gate of the top N-channel synchronous switch MOSFET. The TG driver draws power from the BOOST pin and returns to the SW pin, providing true floating drive to the top MOSFET. BOOST (Pin 27): Top Gate Driver Supply. The BOOST pin supplies power to the floating TG driver. BOOST should be bypassed to SW with a low ESR (X5R or better) 0.1F capacitor. An additional fast recovery Schottky diode from DRVCC to the BOOST pin will create a complete floating charge-pumped supply at BOOST. ION (Pin 31): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. SGND (Pin 33): Signal Ground. All small signal components should connect to this ground and eventually connect to PGND at one point. 38105f 10 LTC3810-5 FUNCTIONAL DIAGRAM INTVCC EXTVCC NDRV INTVCC VIN 5.5V 5V REG VIN RUV1 UVIN 14 RUV2 9V 0.8V REF INTVCC MODE LOGIC + - OFF NDRV 15 M3 - VIN UV UV + INTVCC 4.2V INTVCC 17 EXTVCC 16 + 0.8V MODE/SYNC 7 PLLFLTR - + 10 VON 4 RON VIN ION 1 tON = 1.4V VRNG 5 ITH FOLDBACK FB ITH 8 0.7V UV 2.6V CC2 RC CC1 EA FAULT RUN SHDN OV 4V OVERTEMP SENSE 0.8V 1.5V SS/TRACK 11 SHDN 13 - + -++ + F 270A - PLL-SYNC 1.4A 100nA VVON (76pF) IION R S Q - - TIMEOUT LOGIC DRV OFF FCNT ON 5.5V ON + + DB VIN + - 4.7V BOOST 28 TG 27 SW 26 SENSE+ 25 DRVCC CB M1 + CIN + ICMP 20k + IREV SWITCH LOGIC L1 VOUT - - SHDN OV 18 BG 19 BGRTN CVCC M2 + COUT x 20 SENSE- 21 PGOOD 6 RFB1 + - 0.74V VFB 9 + SGND 12 RFB2 - 0.86V 38105 FD 38105f 11 LTC3810-5 OPERATION Main Control Loop The LTC3810-5 is a current mode controller for DC/DC step-down converters. In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer (OST). When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the SENSE- and SENSE+ pins using a sense resistor or the bottom MOSFET onresistance. The voltage on the ITH pin sets the comparator threshold corresponding to the inductor valley current. The fast 25MHz error amplifier EA adjusts this voltage by comparing the feedback signal VFB to the internal 0.8V reference voltage. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an on time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor RON. For applications with stringent constant frequency requirements, the LTC3810-5 can be synchronized with an external clock. By programming the nominal frequency the same as the external clock frequency, the LTC3810-5 PULSE SKIP MODE FORCED CONTINUOUS behaves as a constant frequency part against the load and supply variations. Pulling the SHDN pin low forces the controller into its shutdown state, turning off both M1 and M2. Forcing a voltage above 1.5V will turn on the device. Pulse Skip Mode The LTC3810-5 can operate in one of two modes selectable with the MODE/SYNC pin--pulse skip mode or forced continuous mode (see Figure 1). Pulse skip mode is selected when increased efficiency at light loads is desired (see Figure 2). In this mode, the bottom MOSFET is turned off when inductor current reverses to minimize efficiency loss due to reverse current flow and gate charge switching. At low load currents, ITH will drop below the zero current level (1.2V) shutting off both switches. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level to initiate another cycle. In this mode, frequency is proportional to load current at light loads. Pulse skip mode operation is disabled by comparator F when the MODE/SYNC pin is brought below 0.8V, forcing continuous synchronous operation. Forced continuous mode is less efficient due to resistive losses, but has the advantage of better transient response at low currents, approximately constant frequency operation, and the ability to maintain regulation when sinking current. 100 90 80 PULSE SKIP 0A DECREASING LOAD CURRENT 0A 0A EFFICIENCY (%) 70 60 50 40 30 20 10 VIN = 12V VIN = 42V 0.1 LOAD (A) 1 10 38105 F02 FORCED CONTINUOUS 0A 0A 0A 38105 F01 0 0.01 Figure 1. Comparison of Inductor Current Waveforms for Pulse Skip Mode and Forced Continuous Operation Figure 2. Efficiency in Pulse Skip/ Forced Continuous Modes 38105f 12 LTC3810-5 OPERATION Fault Monitoring/Protection Constant on-time current mode architecture provides accurate cycle-by-cycle current limit protection--a feature that is very important for protecting the high voltage power supply from output short-circuits. The cycle-by-cycle current monitor guarantees that the inductor current will never exceed the value programmed on the VRNG pin. Foldback current limiting provides further protection if the output is shorted to ground. As VFB drops, the buffered current threshold voltage ITHB is pulled down and clamped to 1V. This reduces the inductor valley current level to one-sixth of its maximum value as VFB approaches 0V. Foldback current limiting is disabled at start-up. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a 10% window around the regulation point after the internal 120s power bad mask timer expires. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on immediately and held on until the overvoltage condition clears. The LTC3810-5 provides two undervoltage lockout comparators--one for the INTVCC/DRVCC supply and one for the input supply VIN. The INTVCC UV threshold is 4.2V to guarantee that the MOSFETs have sufficient gate drive voltage before turning on. The VIN UV threshold (UVIN pin) is 0.8V with 10% hysteresis which allows programming the VIN threshold with the appropriate resistor divider connected to VIN. If either comparator inputs are under the UV threshold, the LTC3810-5 is shut down and the drivers are turned off. Strong Gate Drivers The LTC3810-5 contains very low impedance drivers capable of supplying amps of current to slew large MOSFET gates quickly. This minimizes transition losses and allows paralleling MOSFETs for higher current applications. A 60V floating high side driver drives the top side MOSFET and a low side driver drives the bottom side MOSFET (see Figure 3). The bottom side driver is supplied directly from the DRVCC pin. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode from DRVCC when the top MOSFET turns off. In pulse skip mode operation, where it is possible that the bottom MOSFET will be off for an extended period of time, an internal timeout guarantees that the bottom MOSFET is turned on at least once every 25s for one on-time period to refresh the bootstrap capacitor. The bottom driver has an additional feature that helps minimize the possibility of external MOSFET shoot-thru. When the top MOSFET turns on, the switch node dV/dt pulls up the bottom MOSFET's internal gate through the Miller capacitance, even when the bottom driver is holding the gate terminal at ground. If the gate is pulled up high enough, shoot-thru between the top side and bottom side MOSFETs can occur. To prevent this from occurring, the bottom driver return is brought out as a separate pin (BGRTN) so that a negative supply can be used to reduce the effect of the Miller pull-up. For example, if a -2V supply is used on BGRTN, the switch node dV/dt could pull the gate up 2V before the VGS of the bottom MOSFET has more than 0V across it. DRVCC VIN LTC3810-5 DRVCC DB BOOST TG SW CB M1 L + CIN VOUT BG BGRTN 0V TO -5V 38105 F03 M2 + COUT Figure 3. Floating TG Driver Supply and Negative BG Return IC/Driver Supply Power The LTC3810-5's internal control circuitry and top and bottom MOSFET drivers operate from a supply voltage (INTVCC, DRVCC pins) in the range of 4.5V to 14V. The LTC3810-5 has two integrated linear regulator controllers to easily generate this IC/driver supply from either the high voltage input or from the output voltage. For best efficiency the supply is derived from the input voltage during start-up and then derived from the lower voltage output as soon as the output is higher than 4.7V. Alternatively, the supply can be derived from the input continuously if the output is 38105f 13 LTC3810-5 OPERATION < 4.7V or an external supply in the appropriate range can be used. The LTC3810-5 will automatically detect which mode is being used and operate properly. The four possible operating modes for generating this supply are summarized as follows (see Figure 4): 1. LTC3810-5 generates a 5.5V start-up supply from a small external SOT23 N-channel MOSFET acting as linear regulator with drain connected to VIN and gate controlled by the LTC3810-5's internal linear regulator controller through the NDRV pin. As soon as the output voltage reaches 4.7V, the 5.5V IC/driver supply is derived from the output through an internal low-dropout regulator to optimize efficiency. If the output is lost due to a short, the LTC3810-5 goes through repeated low duty cycle soft-start cycles (with the drivers shut off in between) to attempt to bring up the output without burning up the SOT23 MOSFET. This scheme eliminates the long start-up times associated with a conventional trickle charger by using an external MOSFET to quickly charge the IC/driver supply capacitors (CINTVCC, CDRVCC). 2. Similar to (1) except that the external MOSFET is used for continuous IC/driver power instead of just for startMode 1: MOSFET for Startup Only VIN I > 270A I < 270A up. The MOSFET is sized for proper dissipation and the driver shutdown/restart for VOUT < 4.7V is disabled. This scheme is less efficient but may be necessary if VOUT < 4.7V and a boost network is not desired. 3. Trickle charge mode provides an even simpler approach by eliminating the external MOSFET. The IC/driver supply capacitors are charged through a single high-valued resistor connected to the input supply. When the INTVCC voltage reaches the turn-on threshold of 9V (automatically raised from 4.7V to provide extra headroom for start-up), the drivers turn on and begin charging up the output capacitor. When the output reaches 4.7V, IC/driver power is derived from the output. In trickle-charge mode, the supply capacitors must have sufficient capacitance such that they are not discharged below the 4V INTVCC UV threshold before the output is high enough to take over or else the power supply will not start. 4. Low voltage supply available. The simplest approach is if a low voltage supply (between 4.5V and 14V) is available and connected directly to the IC/driver supply pins. Mode 2: MOSFET for Continuous Use VIN NDRV INTVCC LTC3810-5 NDRV + 5.5V INTVCC LTC3810-5 + 5.5V EXTVCC VOUT (> 4.7V) EXTVCC Mode 3: Trickle Charge Mode VIN Mode 4: External Supply NDRV INTVCC LTC3810-5 NDRV + 5.5V INTVCC LTC3810-5 + + - 4.5V to 14V EXTVCC VOUT EXTVCC 38105 F04 Figure 4. Operating Modes for IC/Driver Supply 38105f 14 LTC3810-5 APPLICATIO S I FOR ATIO The basic LTC3810-5 application circuit is shown on the first page of this data sheet. External component selection is primarily determined by the maximum input voltage and load current and begins with the selection of the sense resistance and power MOSFET switches. The LTC3810-5 uses either a sense resistor or the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Next, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Finally, loop compensation components are selected to meet the required transient/phase margin specifications. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across a sense resistance that appears between the SENSE- and SENSE+ pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately: VSENSE(MAX) = 0.173VRNG - 0.026 The current mode control loop will not allow the inductor current valleys to exceed VSENSE(MAX)/RSENSE. In practice, one should allow some margin for variations in the LTC3810-5 and external component values and a good guide for selecting the sense resistance is: VSENSE(MAX ) R SENSE = 1 . 3 * IOUT(MAX ) An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 60mV to 320mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 95mV or 215mV, respectively. Connecting the SENSE+ and SENSE- Pins The LTC3810-5 can be used with or without a sense resistor. When using a sense resistor, place it between the source of the bottom MOSFET, M2, and PGND. Connect the SENSE+ and SENSE- pins to the top and bottom of T NORMALIZED ON-RESISTANCE U the sense resistor. Using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the bottom MOSFET as the current sense element by simply connecting the SENSE+ pin to the lower MOSFET drain and SENSE - pin to the MOSFET source. This improves efficiency, but one must carefully choose the MOSFET on-resistance, as discussed below. Power MOSFET Selection The LTC3810-5 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage BVDSS, threshold voltage V(GS)TH, on-resistance RDS(ON), input capacitance and maximum current IDS(MAX). When the bottom MOSFET is used as the current sense element, particular attention must be paid to its on-resistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: RDS(ON)(MAX ) = R SENSE T The T term is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature (see Figure 5) and typically varies from 0.4%/C to 1.0%/C depending on the particular MOSFET used. 2.0 1.5 1.0 0.5 0 - 50 50 100 0 JUNCTION TEMPERATURE (C) 150 38105 F05 W U U Figure 5. RDS(ON) vs Temperature 38105f 15 LTC3810-5 APPLICATIO S I FOR ATIO The most important parameter in high voltage applications is breakdown voltage BVDSS. Both the top and bottom MOSFETs will see full input voltage plus any additional ringing on the switch node across its drain-to-source during its off-time and must be chosen with the appropriate breakdown specification. The LTC3810-5 is designed to be used with a 4.5V to 14V gate drive supply (DRVCC pin) for driving logic-level MOSFETs (VGS(MIN) 4.5V). For maximum efficiency, on-resistance RDS(ON) and input capacitance should be minimized. Low RDS(ON) minimizes conduction losses and low input capacitance minimizes transition losses. MOSFET input capacitance is a combination of several components but can be taken from the typical "gate charge" curve included on most data sheets (Figure 6). VIN MILLER EFFECT VGS a QIN CMILLER = (QB - QA)/VDS b V + VGS +V DS - 38105 F06 - Figure 6. Gate Charge Characteristic The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET 16 U data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: MainSwitchDutyCycle = VOUT VIN VIN - VOUT VIN SynchronousSwitch DutyCycle = The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: PTOP = VOUT (IMAX )2 ( T )RDS(ON) + VIN I VIN 2 MAX (RDR )(CMILLER ) * 2 1 1 + ( f) VCC - VTH(IL) VTH(IL ) V - VOUT = IN (IMAX )2( T )RDS(0N) VIN PBOT where T is the temperature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2 at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. VTH(IL) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I2R losses while the topside N-channel equation incudes an additional term for transition losses, which peak at the highest input voltage. For high input voltage low duty cycle applications that are typical for the LTC3810-5, transition losses are the dominate loss term and therefore using higher RDS(ON) device with lower CMILLER usually provides the highest efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. Since there is no transition loss 38105f W U U LTC3810-5 APPLICATIO S I FOR ATIO term in the synchronous MOSFET, optimal efficiency is obtained by minimizing RDS(ON) --by using larger MOSFETs or paralleling multiple MOSFETS. Multiple MOSFETs can be used in parallel to lower RDS(ON) and meet the current and thermal requirements if desired. The LTC3810-5 contains large low impedance drivers capable of driving large gate capacitances without significantly slowing transition times. In fact, when driving MOSFETs with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (10 or less) to reduce noise and EMI caused by the fast transitions. Operating Frequency The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. The operating frequency of LTC3810-5 applications is determined implicitly by the one-shot timer that controls the on-time tON of the top MOSFET switch. The on-time is set by the current out of the ION pin and the voltage at the VON pin according to: t ON = VVON (76pF) IION 1000 VOUT = 5V SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) VOUT = 3.3V VOUT = 2.5V VOUT = 1.5V 100 10 100 RON (k) 1000 38105 F07a Figure 7a. Switching Frequency vs RON (VON = 0V) U Tying a resistor RON from VIN to the ION pin yields an on-time inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency operation as the input supply varies: f= VOUT [HZ ] VVON * RON(76pF) To hold frequency constant during output voltage changes, tie the VON pin to VOUT or to a resistive divider from VOUT when VOUT > 2.4V. The VON pin has internal clamps that limit its input to the one-shot timer. If the pin is tied below 0.7V, the input to the one-shot is clamped at 0.7V. Similarly, if the pin is tied above 2.4V, the input is clamped at 2.4V. In high VOUT applications, tie VON to INTVCC. Figures 7a and 7b show how RON relates to switching frequency for several common output voltages. Changes in the load current magnitude will cause frequency shift. Parasitic resistance in the MOSFET switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. By lengthening the on-time slightly as current increases, constant frequency operation can be maintained. This is accomplished with a resistive divider from the ITH pin to the VON pin and VOUT. The values required will depend on the parasitic resistances in the specific application. A good starting point is to feed about 25% of the voltage change at the ITH pin to the VON pin as shown in Figure 8. Place capacitance on the VON pin to filter out the ITH variations at the switching frequency. 1000 VOUT = 12V VOUT = 3.3V VOUT = 5V 100 10 100 RON (k) 1000 38105 F07b W U U Figure 7b. Switching Frequency vs RON (VON = INTVCC) 38105f 17 LTC3810-5 APPLICATIO S I FOR ATIO INTVCC 5.5V RVON1 100k VON RVON2 30k CVON 0.01F 100k LTC3810-5 ITH 38105 F08 Figure 8. Correcting Frequency Shift with Load Current Changes Minimum Off-Time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3810-5 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 250ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT t ON + t OFF(MIN) t ON A plot of maximum duty cycle vs frequency is shown in Figure 9. 2.0 SWITCHING FREQUENCY (MHz) 1.5 DROPOUT REGION 1.0 0.5 0 0 0.25 0.50 0.75 DUTY CYCLE (VOUT/VIN) 1.0 38105 F09 Figure 9. Maximum Switching Frequency vs Duty Cycle 18 U Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V V IL = OUT 1 - OUT VIN f L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: V VOUT OUT L= 1- VIN(MAX ) f IL(MAX ) Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool M(R) cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Schottky Diode D1 Selection The Schottky diode D1 shown in the front page schematic conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated 38105f W U U LTC3810-5 APPLICATIO S I FOR ATIO for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. Input Capacitor Selection In continuous mode, the drain current of the top MOSFET is approximately a square wave of duty cycle VOUT/VIN which must be supplied by the input capacitor. To prevent large input transients, a low ESR input capacitor sized for the maximum RMS current is given by: V V ICIN(RMS) IO(MAX ) OUT IN - 1 VIN VOUT 1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IO(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. Because tantalum and OS-CON capacitors are not available in voltages above 30V, ceramics or aluminum electrolytics must be used for regulators with input supplies above 30V. Ceramic capacitors have the advantage of very low ESR and can handle high RMS current, but ceramics with high voltage ratings (> 50V) are not available with more than a few microfarads of capacitance. Furthermore, ceramics have high voltage coefficients which means that the capacitance values decrease even more when used at the rated voltage. X5R and X7R type ceramics are recommended for their lower voltage and temperature coefficients. Another consideration when using ceramics is their high Q which, if not properly damped, may result in excessive voltage stress on the power MOSFETs. Aluminum electrolytics have much higher bulk capacitance, but they have higher ESR and lower RMS current ratings. U A good approach is to use a combination of aluminum electrolytics for bulk capacitance and ceramics for low ESR and RMS current. If the RMS current cannot be handled by the aluminum capacitors alone, when used together, the percentage of RMS current that will be supplied by the aluminum capacitor is reduced to approximately: % IRMS,ALUM 1 1 + (8 fCRESR )2 * 100 % where RESR is the ESR of the aluminum capacitor and C is the overall capacitance of the ceramic capacitors. Using an aluminum electrolytic with a ceramic also helps damp the high Q of the ceramic, minimizing ringing. Output Capacitor Selection The selection of COUT is primarily determined by the ESR required to minimize voltage ripple. The output ripple (VOUT) is approximately equal to: 1 VOUT IL ESR + 8 fCOUT Since IL increases with input voltage, the output ripple is highest at maximum input voltage. ESR also has a significant effect on the load transient response. Fast load transitions at the output will appear as voltage across the ESR of COUT until the feedback loop in the LTC3810-5 can change the inductor current to match the new load current value. Typically, once the ESR requirement is satisfied the capacitance is adequate for filtering and has the required RMS current rating. Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo should be considered for high performance throughhole capacitors. The OS-CON (organic semiconductor dielectric) capacitor available from Sanyo has the lowest product of ESR and size of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the effect of their lead inductance. In surface mount applications, multiple capacitors placed in parallel may be required to meet the ESR, RMS current handling and load step requirements. Dry tantalum, special 38105f W U U 19 LTC3810-5 APPLICATIO S I FOR ATIO polymer and aluminum electrolytic capacitors are available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Several excellent surge-tested choices are the AVX, TPS and TPSV or the KEMET T510 series. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-driven applications providing that consideration is given to ripple current ratings and long term reliability. Other capacitor types include Panasonic SP and Sanyo POSCAPs. Output Voltage The LTC3810-5 output voltage is set by a resistor divider according to the following formula: R VOUT = 0 . 8 V 1 + FB1 RFB2 The external resistor divider is connected to the output as shown in the Functional Diagram, allowing remote voltage sensing. The resultant feedback signal is compared with the internal precision 800mV voltage reference by the error amplifier. The internal reference has a guaranteed tolerance of less than 1%. Tolerance of the feedback resistors will add additional error to the output voltage. 0.1% to 1% resistors are recommended. Input Voltage Undervoltage Lockout A resistor divider connected from the input supply to the UVIN pin (see Functional Diagram) is used to program the input supply undervoltage lockout thresholds. When the rising voltage at UVIN reaches 0.88V the LTC3810 turns on, and when the falling voltage at UVIN drops below 0.8V, the LTC3810 is shut down - providing 10% hysterisis. The input voltage UVLO thresholds are set by the resistor divider according to the following formulas: VIN, FALLING = 0.8V (1 + RUV1/RUV2) and VIN, RISING = 0.88V (1 + RUV1/RUV2) 38105f 20 U If input supply undervoltage lockout is not needed, it can be disabled by connecting UVIN to INTVCC. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from DRVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1F to 0.47F, X5R or X7R dielectric capacitor is adequate. The reverse breakdown of the external diode, DB, must be greater than VIN(MAX). Another important consideration for the external diode is the reverse recovery and reverse leakage, either of which may cause excessive reverse current to flow at full reverse voltage. If the reverse current times reverse voltage exceeds the maximum allowable power dissipation, the diode may be damaged. For best results, use an ultrafast recovery diode such as the MMDL770T1. Bottom MOSFET Driver Return Supply (BGRTN) The bottom gate driver, BG, switches from DRVCC to BGRTN where BGRTN can be a voltage between ground and -5V. Why not just keep it simple and always connect BGRTN to ground? In high voltage switching converters, the switch node dV/dt can be many volts/ns, which will pull up on the gate of the bottom MOSFET through its Miller capacitance. If this Miller current, times the internal gate resistance of the MOSFET plus the driver resistance, exceeds the threshold of the FET, shoot-through will occur. By using a negative supply on BGRTN, the BG can be pulled below ground when turning the bottom MOSFET off. This provides a few extra volts of margin before the gate reaches the turn-on threshold of the MOSFET. Be aware that the maximum voltage difference between DRVCC and BGRTN is 14V. If, for example, VBGRTN = -2V, the maximum voltage on DRVCC pin is now 12V instead of 14V. W U U LTC3810-5 APPLICATIO S I FOR ATIO IC/MOSFET Driver Supplies (INTVCC and DRVCC) The LTC3810-5 drivers are supplied from the DRVCC and BOOST pins (see Figure 2), which have an absolute maximum voltage of 14V. Since the main supply voltage, VIN is typically much higher than 14V a separate supply for the IC power (INTVCC) and driver power (DRVCC) must be used. The LTC3810-5 has integrated bias supply control circuitry that allows the IC/driver supply to be easily generated from VIN and/or VOUT with minimal external components. There are four ways to do this as shown in the simplified schematics of Figure 3 and explained in the following sections. Using the Linear Regulator for INTVCC/DRVCC Supply In Mode 1, a small external SOT23 MOSFET, controlled by the NDRV pin, is used to generate a 5.5V start-up supply from VIN. The small SOT23 package can be used because the NMOS is on continuously only during the brief start-up period. As soon as the output voltage reaches 4.7V, the LTC3810-5 turns off the external NMOS and the LTC3810-5 regulates the 5.5V supply from the EXTVCC pin (connected to VOUT or a VOUT derived boost network) through an internal low dropout regulator. For this mode to work properly, EXTVCC must be in the range 4.7V < EXTVCC < 15V. If VOUT < 4.7V, a charge pump or extra winding can be used to raise EXTVCC to the proper voltage, or alternatively, Mode 2 should be used as explained later in this section. If VOUT is shorted or otherwise goes below the minimum 4.5V threshold, the MOSFET connected to VIN is turned back on to maintain the 5.5V supply. However if FAULT TIMEOUT ENABLED SS/TRACK DRIVER POWER FROM VOUT DRIVER POWER FROM VIN EXTVCC UV THRESHOLD DRIVER POWER FROM VIN STARTUP VOUT SHORT-CIRCUIT EVENT START-UP INTO SHORT-CIRCUIT TG/BG 38105 F10 Figure 10. Fault Timeout Operation U the output cannot be brought up within a timeout period, the drivers are turned off to prevent the SOT23 MOSFET from overheating. Soft-start cycles are then attempted at low duty cycle intervals to try to bring the output back up (see Figure 10). This fault timeout operation is enabled by choosing the choosing RNDRV such that the resistor current INDRV is greater than 270A by using the following formulas: RNDRV Where ICC = ( f) Q G(TOP) + Q G(BOTTOM) + 3mA and VTH is the threshold voltage of the MOSFET. The value of R NDRV also affects the V IN(MIN) as follows: VIN(MIN) = VINTVCC(MIN) + (40A) RNDRV +VT (1) where VINTVCC(MIN) is normally 4.5V for driving logic level MOSFETs. If minimum VIN is not low enough, consider reducing RNDRV and/or using a Darlington NPN instead of an NMOS to reduce VT to ~1.4V. When using RNDRV equal to the computed value, the LTC3810-5 will enable the low duty cycle soft-start retries only when the desired maximum power dissipation, PMOSFET(MAX), in the MOSFET is exceeded and leave the drivers on continuously otherwise. The shutoff/restart times are a function of the TRACK/SS capacitor value. PMOSFET(MAX ) / ICC - VTH 270 A W U U ( ) DRIVER OFF THRESHOLD ISS/TRACK = 1.4A (SOURCE) ISS/TRACK = 0.1A (SINK) 38105f 21 LTC3810-5 APPLICATIO S I FOR ATIO The external NMOS for the linear regulator should be a standard 3V threshold type (i.e., not a logic level threshold). The rate of charge of INTVCC from 0V to 5.5V is controlled by the LTC3810-5 to be approximately 75s regardless of the size of the capacitor connected to the INTVCC pin. The charging current for this capacitor is approximately: 5 . 5V IC = CINTVCC 75 s The safe operating area (SOA) for the external NMOS should be chosen so that capacitor charging does not damage the NMOS. Excessive values of capacitor are unnecessary and should be avoided. Typically values in the 1F to 10F work well. One more design requirement for this mode is the minimum soft-start capacitor value. The fault timeout is enabled when SS/TRACK voltage is greater than 4V. This gives the power supply time to bring the output up before it starts the timeout sequence. To prevent timeout sequence from starting prematurely during start-up, a minimum CSS value is necessary to ensure that VSS/TRACK < 4V until VEXTVCC > 4.7V. To ensure this, choose: CSS > COUT * (2.3 x 10-6)/I OUT(MAX) Mode 2 should be used if VOUT is outside of the 4.7V < EXTVCC < 15V operating range and the extra complexity of a charge pump or extra inductor winding is not wanted to boost this voltage above 4.7V. In this mode, EXTVCC is grounded and the NMOS is chosen to handle the worstcase power dissipation: PMOSFET = VIN(MAX ) ( f ) Q G(TOP) + Q G(BOTTOM) + 3mA m ( )( To operate properly, the fault timeout operation must be disabled by choosing RNDRV > (VIN(MAX) - 5.5V - VTH)/270A 22 U If the required RNDRV value results in an unacceptable value for VIN(MIN) (see Equation 1), fault timeout operation can also be disabled by connecting a 500k to 1Meg resistor from SS/TRACK pin to INTVCC. Using Trickle Charge Mode Trickle charge mode is selected by shorting NDRV and INTVCC and connecting EXTVCC to VOUT. Trickle charge mode has the advantage of not requiring an external MOSFET but takes longer to start up due to slow charge up of CINTVCC and CDRVCC through RPULLUP (tDELAY = 0.77 * RPULLUP * CDRVCC) and usually requires larger INTVCC/ DRVCC capacitor values to hold up the supply voltage during start-up. Once the INTVCC/DRVCC voltage reaches the trickle charge UV threshold of 9V, the drivers will turn on and start discharging CINTVCC/CDRVCC at a rate determined by the driver current IG. In order to ensure proper start-up, CINTVCC/CDRVCC must be chosen large enough so that the EXTVCC voltage reaches the switchover threshold of 4.7V before CINTVCC/CDRVCC discharges below the falling UV threshold of 4V. This is ensured if: CINTVCC + CDRVCC > COUT 5.5 * 105 * CSS IG * l arg er of or IMAX VOUT(REG) Where IG is the gate drive current = (f)(QG(TOP) + QG(BOTTOM)) and IMAX is the maximum inductor current selected by VRNG. For RPULLUP, the value should fall in the following range to ensure proper start-up: Min RPULLUP > (VIN(MAX) - 14V)/ICCSR Max RPULLUP < (VIN(MIN) - 9V)/IQ,SHUTDOWN W U U ) 38105f LTC3810-5 APPLICATIO S I FOR ATIO Using an External Supply Connected to the INTVCC/ DRVCC Pins If an external supply is available between 4.5V and 14V, the supply can be connected directly to the INTVCC/DRVCC pins. In this mode, INTVCC, EXTVCC and NDRV must be shorted together. INTVCC/DRVCC Supply and the EXTVCC Connection The LTC3810-5 contains an internal low dropout regulator to produce the 5.5V INTVCC/DRVCC supply from the EXTVCC pin voltage. This regulator turns on when the EXTVCC pin is above 4.7V and remains on until EXTVCC drops below 4.5V. This allows the IC/MOSFET power to be derived from the output or an output derived boost network during normal operation and from the external NMOS from VIN during start-up or short-circuit. Using the EXTVCC pin in this way results in significant efficiency gains compared to what would be possible when deriving this power continuously from the typically much higher VIN voltage. The EXTVCC connection also allows the power supply to be configured in trickle charge mode in which it starts up with a high-valued "bleed" resistor connected from VIN to INTVCC to charge up the INTVCC capacitor. As soon as the output rises above 4.7V the internal EXTVCC regulator takes over before the INTVCC capacitor discharges below the UV threshold. When the EXTVCC regulator is active, the EXTVCC pin can supply up to 50mA RMS. Do not apply more than 15V to the EXTVCC pin. The following list summarizes the possible connections for EXTVCC: 1. EXTVCC grounded. This connection will require INTVCC to be powered continuously from an external NMOS from VIN resulting in an efficiency penalty as high as 10% at high input voltages. U 2. EXTVCC connected directly to VOUT. This is the normal connection for 4.7V < VOUT < 15V and provides the highest efficiency. The power supply will start up using an external NMOS or a bleed resistor until the output supply is available. 3. EXTVCC connected to an output-derived boost network. If VOUT < 4.7V. The low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7V. 4. EXTVCC connected to INTVCC. This is the required connection for EXTVCC if INTVCC is connected to an external supply where the external supply is 4.5V < VEXT < 15V. Applications using large MOSFETs with a high input voltage and high frequency of operation may result in a large EXTVCC pin current. Due to the LTC3810-5 thermally enhanced package, maximum junction temperature will rarely be exceeded, however, it is good design practice to verify that the maximum junction temperature rating and RMS current rating are within the maximum limits. Typically, most of the EXTVCC current consists of the MOSFET gates current. In continuous mode operation, this EXTVCC current is: IEXTVCC = f Q G(TOP) + Q G(BOTTOM) + 3mA < 50mA The junction temperature can be estimated from the equations given in Note 2 of the Electrical Characteristics as follows: TJ = TA + IEXTVCC * (VEXTVCC - VINTVCC)(34C/W) < 125C If absolute maximum ratings are exceeded, consider using an external supply connected directly to the INTVCC pin. W U U ( ) 38105f 23 LTC3810-5 APPLICATIO S I FOR ATIO FEEDBACK LOOP/COMPENSATION Feedback Loop Types In a typical LTC3810-5 circuit, the feedback loop consists of the modulator, the output filter and load, and the feedback amplifier with its compensation network. All of these components affect loop behavior and must be accounted for in the loop compensation. The modulator and output filter consists of the internal current comparator, the output MOSFET drivers and the external MOSFETs, inductor and output capacitor. Current mode control eliminates the effect of the inductor by moving it to the inner loop, reducing it to a first order system. From a feedback loop point of view, it looks like a linear voltage controlled current source from ITH to VOUT and has a gain equal to (IMAXROUT)/1.2V. It has fairly benign AC behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. The external output capacitor and load cause a first order roll off at the output at the ROUTCOUT pole frequency, with the attendant 90 phase shift. This roll off is what filters the PWM waveform, resulting in the desired DC output voltage. The output capacitor also contributes a zero at the COUTRESR frequency which adds back the 90 phase and cancels the first order roll off. So far, the AC response of the loop is pretty well out of the user's control. The modulator is a fundamental piece of the LTC3810-5 design and the external output capacitor is usually chosen based on the regulation and load current requirements without considering the AC loop response. The feedback amplifier, on the other hand, gives us a handle with which to adjust the AC response. The goal is to have 180 phase shift at DC (so the loop regulates), and something less than 360 phase shift (preferably about 300) at the point that the loop gain falls to 0dB, i.e., the crossover frequency, with as much gain as possible at frequencies below the crossover frequency. Since the modulator/output filter is a first order system with maximum of 90 phase shift (at frequencies below fSW/4) and the feedback amplifier adds another 90 of phase shift, some phase boost is required at the crossover frequency to achieve good phase margin. If the ESR zero is below the crossover frequency, this zero may provide enough phase boost to achieve the desired phase margin and the only IN RFB1 FB RFB2 VREF R2 C1 GAIN (dB) C3 RFB1 R3 FB R2 C1 GAIN (dB) 24 U requirement of the compensation will be to guarantee that the gain is below zero at frequencies above fSW/4. If the ESR zero is above the crossover frequency, the feedback amplifier will probably be required to provide phase boost. For most LTC3810-5 applications, Type 2 compensation will provide enough phase boost; however some applications where high bandwidth is required with low ESR ceramics and lots of bulk capacitance, Type 3 compensation may be necessary to provide additional phase boost. The two types of compensation networks, "Type 2" and "Type 3" are shown in Figures 11 and 12. When component values are chosen properly, these networks provide a "phase bump" at the crossover frequency. Type 2 uses a single pole-zero pair to provide up to about 60 of phase boost while Type 3 uses two poles and two zeros to provide up to 150 of phase boost. C2 PHASE (DEG) -6dB/OCT GAIN -6dB/OCT FREQ -90 PHASE -180 -270 -360 38105 F11 W U U - OUT 0 + Figure 11. Type 2 Schematic and Transfer Function IN C2 PHASE (DEG) -6dB/OCT GAIN +6dB/OCT -6dB/OCT - OUT 0 RFB2 VREF FREQ -90 PHASE -180 -270 -360 38105 F12 + Figure 12. Type 3 Schematic and Transfer Function 38105f LTC3810-5 APPLICATIO S I FOR ATIO Feedback Component Selection Selecting the R and C values for a typical Type 2 or Type 3 loop is a nontrivial task. The applications shown in this data sheet show typical values, optimized for the power components shown. They should give acceptable performance with similar power components, but can be way off if even one major power component is changed significantly. Applications that require optimized transient response will require recalculation of the compensation values specifically for the circuit in question. The underlying mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover frequency. Modulator gain and phase can be obtained in one of three ways: measured directly from a breadboard, or if the appropriate parasitic values are known, simulated or generated from the modulator transfer function. Measurement will give more accurate results, but simulation or transfer function can often get close enough to give a working system. To measure the modulator gain and phase directly, wire up a breadboard with an LTC3810-5 and the actual MOSFETs, inductor and input and output capacitors that the final design will use. This breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the LTC3810-5, no long wires connecting components, appropriately sized ground returns, etc. Wire the feedback amplifier with a 0.1F feedback capacitor from ITH to FB and a 10k to 100k resistor from VOUT to FB. Choose the bias resistor (RFB2) as required to set the desired output voltage. Disconnect RFB2 from ground and connect it to a signal generator or to the source output of a network analyzer to inject a test signal into the loop. Measure the gain and phase from the ITH pin to the output node at the positive terminal of the output capacitor. Make sure the analyzer's input is AC coupled so that the DC voltages present at both the ITH and VOUT nodes don't corrupt the measurements or damage the analyzer. U If breadboard measurement is not practical, a SPICE simulation can be used to generate approximate gain/ phase curves. Plug the expected capacitor, inductor and MOSFET values into the following SPICE deck and generate an AC plot of VOUT/VITH with gain in dB and phase in degrees. Refer to your SPICE manual for details of how to generate this plot. *3810-5 modulator gain/phase *2006 Linear Technology *this file simulates a simplified model of *the LTC3810-5 for generating a v(out)/ v(ith) *bode plot .param rdson=.0135 ;MOSFET rdson .param Vrng=2 ;use 1.4 for INTVCC and 0.7 for ground .param vsnsmax={0.173*Vrng-0.026} .param Imax={vsnsmax/rdson} .param DL=4 ;inductor ripple current *inductor current gl out 0 value={(v(ith)-1.2)*Imax/1.2+DL/2} *output cap cout out out2 270u ;capacitor value resr out2 0 0.018 ;capacitor ESR *load Rout out 0 2 ; load resistor vstim ith 0 0 ac 1 ;ac stimulus .ac dec 100 100 10meg .probe .end W U U Mathematical software such as MATHCAD or MATLAB can also be used to generate plots using the following transfer function of the modulator: VSENSE(MAX ) H(s) = 1.2 * RDS(ON) s = j2f 1+ s * RESR * COUT * * RL (2) 1+ s * RL * COUT 38105f 25 LTC3810-5 APPLICATIO S I FOR ATIO With the gain/phase plot in hand, a loop crossover frequency can be chosen. Usually the curves look something like Figure 13. Choose the crossover frequency about 25% of the switching frequency for maximum bandwidth. Although it may be tempting to go beyond fSW/4, remember that significant phase shift occurs at half the switching frequency that isn't modeled in the above H(s) equation and PSPICE code. Note the gain (GAIN, in dB) and phase (PHASE, in degrees) at this point. The desired feedback amplifier gain will be -GAIN to make the loop gain at 0dB at this frequency. Now calculate the needed phase boost, assuming 60 as a target phase margin: BOOST = - (PHASE + 30) If the required BOOST is less than 60, a Type 2 loop can be used successfully, saving two external components. BOOST values greater than 60 usually require Type 3 loops for satisfactory performance. Finally, choose a convenient resistor value for RFB1 (10k is usually a good value). Now calculate the remaining values: (K is a constant used in the calculations) f = chosen crossover frequency G = 10(GAIN/20) (this converts GAIN in dB to G in absolute gain) TYPE 2 Loop: BOOST K = tan + 45 2 1 C2 = 2 * f * G * K * RFB1 C1= C2 K2 - 1 R2 = GAIN (dB) ( ) K 2 * f * C1 V (R ) RFB2 = REF FB1 VOUT - VREF 26 U PHASE (DEG) GAIN 0 0 PHASE -90 -180 FREQUENCY (Hz) 38105 F13 W U U Figure 13. Transfer Function of Buck Modulator TYPE 3 Loop: BOOST K = tan2 + 45 4 1 C2 = 2 * f * G * RFB1 C1= C2 (K - 1) K 2 * f * C1 RFB1 R3 = K-1 1 C3 = 2f K * R3 V (R ) RB = REF FB1 VOUT - VREF R2 = SPICE or mathematical software can be used to generate the gain/phase plots for the compensated power supply to do a sanity check on the component values before trying them out on the actual hardware. For software, use the following transfer function: T(s) = A(s)H(s) 38105f LTC3810-5 APPLICATIO S I FOR ATIO Type 2: A (s) = 1+ s * R3 * C2 C2 * C3 s * RFB1 * (C2 + C3) * 1+ s * R3 * C2 + C3 where H(s) was given in Equation 2 and A(s) depends on compensation circuit used: Type 3: A (s) = 1 * s * RFB1 * (C2 + C3) (1+ s * (RFB1 + R3) * C3) * (1+ s * R2 * C1) C1 * (1+ s * R3 * C3) * 1+ s * R2 * C1+ C2 C2 For SPICE, replace VSTIM line in the previous PSPICE code with following code and generate a gain/phase plot of V(out)/V(outin): rfb1 outin vfb 52.5k rfb2 vfb 0 10k eithx ithx 0 laplace {0.8-v(vfb)} = {1/(1+s/1000)} eith ith 0 value={limit(1e6*v(ithx),0,2.4)} cc1 ith vfb 4p cc2 ith x1 8p rc x1 vfb 210k rf outin x2 11k ;delete this line for Type 2 cf x2 vfb 120p ;delete this line for Type 2 vstim out outin dc=0 ac=1m + VIN TG LTC3810-5 SW R4 FCB R3 SGND BG PGND Figure 14. Secondary Output Loop 38105f * U Pulse Skip Mode Operation and MODE/SYNC Pin The MODE/SYNC pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.8V threshold enables pulse skip mode operation where the bottom MOSFET turns off when inductor current reverses. The load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in VIN. Tying the MODE/SYNC pin below the 0.8V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. To prevent forcing current back into the main power supply, potentially boosting the input supply to a dangerous voltage level, forced continuous mode of operation is disabled when the TRACK/SS voltage is below the reference voltage during soft-start or tracking. During these two periods, the PGOOD signal is forced low. In addition to providing a logic input to force continuous operation, the MODE/SYNC pin provides a mean to maintain a flyback winding output when the primary is operating in pulse skip mode. The secondary output VOUT2 is normally set as shown in Figure 14 by the turns ratio N of the transformer. However, if the controller goes into pulse skip mode and halts switching due to a light primary load current, then VOUT2 will droop. An external resistor divider from VOUT2 to the MODE/SYNC pin sets a minimum VIN CIN 1N4148 W U U + T1 1:N *+ VOUT2 COUT2 1F VOUT1 COUT 38105 F14 27 LTC3810-5 APPLICATIO S I FOR ATIO R4 VOUT 2(MIN) = 0 . 8 V 1 + R3 Table 1. MODE/SYNC PIN DC Voltage: 0V to 0.75V DC Voltage: 0.85V Feedback Resistors Ext. Clock OV to 2V CONDITION Forced Continuous Current Reversal Enabled Pulse Skip Mode Operation No Current Reversal Regulating a Secondary Winding Forced Continuous Current Reversal Enabled voltage VOUT2(MIN) below which continuous operation is forced until VOUT2 has risen above its minimum. Fault Conditions: Current Limit and Foldback The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3810-5, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSNS(MAX ) RDS(ON) 1 + IL T 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET on-resistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) 28 U lies the same percentage below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. To further limit current in the event of a short-circuit to ground, the LTC3810-5 includes foldback current limiting. If the output falls by more than 50%, then the maximum sense voltage is progressively lowered to about one tenth of its full value. Be aware also that when the fault timeout is enabled for the external NMOS regulator, an over current limit may cause the output to fall below the minimum 4.5V UV threshold. This condition will cause a linear regulator timeout/restart sequence as described in the Linear Regulator Timeout section if this condition persists. Soft-Start and Tracking The LTC3810-5 has the ability to either soft-start by itself with a capacitor or track the output of another supply. When the device is configured to soft-start by itself, a capacitor should be connected to the TRACK/SS pin. The LTC3810-5 is put in a low quiescent current shutdown state (IQ ~240A) if the SHDN pin voltage is below 1.5V. The TRACK/SS pin is actively pulled to ground in this shutdown state. Once the SHDN pin voltage is above 1.5V, the LTC3810-5 is powered up. A soft-start current of 1.4A then starts to charge the soft-start capacitor CSS. Note that soft-start is achieved not by limiting the maximum output current of the controller but by controlling the ramp rate of the output voltage. Current foldback is disabled during this soft-start phase. During the soft-start phase, the LTC38105 is ramping the reference voltage until it reaches 0.8V. The force continuous mode is also disabled and PGOOD signal is forced low during this phase. The total soft-start time can be calculated as: tSOFTSTART = 0.8 * CSS/1.4A When the device is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TRACK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply output voltage. 38105f W U U LTC3810-5 APPLICATIO S I FOR ATIO Output Voltage Tracking The LTC3810-5 allows the user to program how its output ramps up by means of the TRACK/SS pin. Through this pin, the output can be set up to either coincidentally or ratiometrically track with another supply's output, as shown in Figure 15. In the following discussions, VOUT1 refers to the master LTC3810-5's output and VOUT2 refers to the slave LTC3810-5's output. VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE TIME (15a) Coincident Tracking Figure 15. Two Different Modes of Output Voltage Tracking VOUT1 R3 TO TRACK/SS2 PIN R4 R2 R1 TO VFB1 PIN TO VFB2 PIN R4 R3 TO TRACK/SS2 PIN R2 VOUT2 VOUT1 R1 TO VFB1 PIN TO VFB2 PIN R4 38105 F16 (16a) Coincident Tracking Setup Figure 16. Setup for Coincident and Ratiometric Tracking TRACK/SS2 0.8V VFB2 D3 Figure 17. Equivalent Input Circuit of Error Amplifier U To implement the coincident tracking in Figure 15a, connect an additional resistive divider to VOUT1 and connect its midpoint to the TRACK/SS pin of the slave IC. The ratio of this divider should be selected the same as that of the slave IC's feedback divider shown in Figure 16. In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking, the ratio of the divider should be exactly the same as the master IC's feedback divider. Note that the internal soft-start current will introduce a small VOUT1 VOUT2 VOUT2 TIME 38105 F15 W U U (15b) Ratiometric Tracking VOUT2 R3 (16b) Ratiometric Tracking Setup I I + D1 D2 EA2 - 38105 F17 38105f 29 LTC3810-5 APPLICATIO S I FOR ATIO error on the tracking voltage depending on the absolute values of the tracking resistive divider. By selecting different resistors, the LTC3810-5 can achieve different modes of tracking including the two in Figure 15. So which mode should be programmed? While either mode in Figure 15 satisfies most practical applications, there do exist some tradeoffs. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. This can be better understood with the help of Figure 17. At the input stage of the slave IC's error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. The top two current sources are of the same amplitude. In the coincident mode, the TRACK/SS voltage is substantially higher than 0.8V at steady state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB2 and the internal precision 0.8V reference. In the ratiometric mode, however, TRACK/SS equals 0.8V at steady state. D1 will divert part of the bias current to make VFB2 slightly lower than 0.8V. Although this error is minimized by the exponential I-V characteristic of the diode, it does impose a finite amount of output voltage deviation. Furthermore, when the master IC's output experiences dynamic excursion (under load transient, for example), the slave IC output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. Phase-Locked Loop and Frequency Synchronization The LTC3810-5 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is 30% around the center frequency fO. The center frequency is the operating frequency discussed in the Operating Frequency section. The LTC3810-5 incorporates a pulse detection circuit that will detect a clock on the MODE/SYNC pin. In turn, it will turn on the phase-locked loop function. The pulse width of the clock has to be greater than 400ns and the amplitude of the clock should be greater than 2V. PLLIN DIGITAL PHASE/ FREQUENCY DETECTOR 30 U The internal oscillator locks to the external clock after the second clock transition is received. When external synchronization is detected, LTC3810-5 will operate in forced continuous mode. If an external clock transition is not detected for three successive periods, the internal oscillator will revert to the frequency programmed by the RON resistor. During the start-up phase, phase-locked loop function is disabled. When LTC3810-5 is not in synchronization mode, PLLFLTR pin voltage is set to around 1.215V. Frequency synchronization is accomplished by changing the internal on-time current according to the voltage on the PLLFLTR pin. The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal pulses. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, fH, is equal to the capture range, fC: fH = fC = 0.3 fO The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. A simplified block diagram is shown in Figure 18. RLP 2.4V CLP PLLFLTR VCO 38105 F18 W U U Figure 18. Phase-Locked Loop Block Diagram If the external frequency (fPLLIN) is greater than the oscillator frequency fO, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than fO, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies 38105f LTC3810-5 APPLICATIO S I FOR ATIO are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The LTC3810-5 PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 0.01F to 0.1F. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3810-5 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01 and RL = 0.005, the loss will range from 15mW to 1.5W as the output current varies from 1A to 10A. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant U at input voltages above 20V and can be estimated from the second term of the PMAIN equation found in the Power MOSFET Selection section. When transition losses are significant, efficiency can be improved by lowering the frequency and/or using a top MOSFET(s) with lower CRSS at the expense of higher RDS(ON). 3. INTVCC/DRVCC current. This is the sum of the MOSFET driver and control currents. Control current is typically about 3mA and driver current can be calculated by: IGATE = f(QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT) are the gate charges of the top and bottom MOSFETs. This loss is proportional to the supply voltage that INTVCC/ DRVCC is derived from, i.e., VIN for the external NMOS linear regulator, VOUT for the internal EXTVCC regulator, or VEXT when an external supply is connected to INTVCC/DRVCC. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During 38105f W U U 31 LTC3810-5 APPLICATIO S I FOR ATIO this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Design Example As a design example, take a supply with the following specifications: VIN = 12V to 60V, VOUT = 5V 5%, IOUT(MAX) = 6A, f = 250kHz. First, calculate the timing resistor: RON = 5V = 110k 2 . 4V * 250kHz * 76pF and choose the inductor for about 40% ripple current at the maximum VIN: L= 5V 5V 1- 60 V = 7 . 6 H 250kHz * 0 . 4 * 6 A With a 7.7H inductor, ripple current will vary from 1.5A to 2.4A (25% to 40%) over the input supply range. Next, choose the bottom MOSFET switch. Since the drain of the MOSFET will see the full supply voltage 60V (max) plus any ringing, choose an 60V MOSFET. The Si7850DP has: BVDSS = 60V RDS(ON) = 31m (max)/25m (nom), = 0.007/C, CMILLER = (8.3nC - 2.8nC)/30V = 183pF, VGS(MILLER) = 3.8V, JA= 22C/W. This yields a nominal sense voltage of: VSNS(NOM) = 6A * 1.3 * 0.025 = 195mV To guarantee proper current limit at worst-case conditions, increase nominal VSNS by at least 50% to 320mV (by tying VRNG to 2V). To check if the current limit is acceptable at VSNS = 320mV, assume a junction temperature of about 55C above a 70C ambient (125C = 1.7): ILIMIT 320mV 1 + * 2 . 4A = 7 . 3A 1 . 7 * 0 . 031 2 32 U and double-check the assumed TJ in the MOSFET: PBOT = 60 V - 5V * 7 . 3A 2 * 1 . 7 * 0 . 031 = 2 . 6 W 60 V TJ = 70C + 2.6W * 22C/W = 127C Verify that the Si7850DP is also a good choice for the top MOSFET by checking its power dissipation at current limit and maximum input voltage, assuming a junction temperature of 30C above a 70C ambient (100C = 1.5): PMAIN = 5V * 7 . 3A 2 (1 . 5 * 0 . 031 ) 60 V 1 1 7 . 3A + 60 V 2 * * 250kHz * 2 * 183pF * + 5V - 3 . 8 V 3 . 8 V 2 = 0 . 206 W + 1 . 32W = 1 . 53W W U U TJ = 70C + 1.53W * 22C/W = 104C The junction temperature will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in this circuit. Since VOUT > 4.7V, the INTVCC voltage can be generated from VOUT with the internal LDO by connecting VOUT to the EXTVCC pin. A small SOT23 MOSFET such as the ZXMN10A07F can be used for the pass device if fault timeout is enabled. Choose RNDRV to guarantee that fault timeout is enabled when power dissipation of M3 exceeds 0.4W (max for 70C ambient): ICC = 250kHz * 2 * 18nC + 3mA = 12mA RNDRV 0.4W / 0.012A - 3V = 112k 270A So, choose RNDRV = 100k. CIN is chosen for an RMS current rating of about 3A at 85C. The output capacitors are chosen for a low ESR of 0.018 to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: VOUT(RIPPLE) = IL(MAX) * ESR = 2.4A * 0.018 = 43mV 38105f LTC3810-5 APPLICATIO S I FOR ATIO VOUT(STEP) = ILOAD * ESR = 6A * 0.018 = 108mV An optional 10F ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 19. PC Board Layout Checklist When laying out a PC board follow one of two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. * The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. * Place CIN, COUT, MOSFETs, D1 and inductor all in one compact area. It may help to have some components on the bottom side of the board. * Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3810-5. Use several bigger vias for power components. * Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI down. * Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. However, a 0A to 6A load step will cause an output change of up to: U * Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. * Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. * Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short. * Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. * Keep the high dV/dt SW, BOOST and TG nodes away from sensitive small-signal nodes. * Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and SGND pins. * Connect the top driver boost capacitor CB closely to the BOOST and SW pins. * Connect the bottom driver decoupling capacitor CDRVCC closely to the DRVCC and BGRTN pins. 38105f W U U 33 LTC3810-5 APPLICATIO S I FOR ATIO RON 110k CON 100pF 1 40.2k 4 60.4k PGOOD 250kHz CLOCK 0.01F RUV1 200k 10k ION VON LTC3810 BOOST CSS 1000pF 5V RNG 6 PGOOD 7 MODE_SYNC 8 ITH 9 VFB 10 PLL/LPF 11 SHDN SS/TRACK 12 SGND 13 SHDN 14 UVIN SGND RUV2 14.3k RFB2 1.91k CC2 47pF RC 200k CC1 5pF Figure 19. 12V to 60V Input Voltage to 5V/6A Synchronized at 250kHz TYPICAL APPLICATIONS 7V to 60V Input Voltage to 5V/5A with IC Power from 12V Supply and All Ceramic Output Capacitors CIN1 68F 100V VIN 7V to 60V CIN2 1F 100V PGND RON 110k CON 100pF 1 ION LTC3810-5 28 BOOST TG 27 26 SW 25 SENSE+ 4 5 6 7 8 9 10 CSS 1000pF 11 VON VRNG PGOOD MODE_SYNC ITH VFB PLL/LPF PGOOD RUV1 470k SHDN SS/TRACK 12 SGND 13 SHDN 14 UVIN SGND RUV2 61.9k RFB2 1.91k CC2 47pF RC 100k CC1 5pF 34 U RNDRV 100k M3 ZXMN10A07F DB BAS19 28 CB 0.1F M1 Si7852DP CIN1 68F 100V VIN 12V to 60V CIN2 1F 100V PGND 27 TG 26 SW 25 SENSE+ SENSE - 21 W U U L1 10H BGRTN 20 CDRVCC 0.1F COUT1 270F 6.3V D1 B1100 CVCC 1F C5 1F PGND VOUT 5V 6A 19 BG 18 DRVCC 17 INTVCC 16 EXTVCC 15 NDRV M2 Si7852DP 10 COUT2 10F 6.3V RFB1 10k 38105 F19 12V DB BAS19 CB 0.1F M1 Si7850DP SENSE - 21 L1 4.7H BGRTN 20 CDRVCC 0.1F COUT 47F 6.3V x3 D1 B1100 CVCC 1F C5 22F PGND VOUT 5V 5A 19 BG 18 DRVCC 17 INTVCC 16 EXTVCC 15 NDRV 10 M2 Si7850DP RFB1 10k 38105 TA03 38105f LTC3810-5 TYPICAL APPLICATIONS 15V to 60V Input Voltage to 3.3V/5A with Fault Timeout, Pulse Skip and VIN UV Disabled RNDRV 274k M3 ZVN4210G DB BAS19 CB 0.1F CIN1 68F 100V VIN 15V to 60V CIN2 1F 100V PGND RON 71.5k CON 100pF 1 ION LTC3810-5 28 BOOST TG 27 PGOOD 4 5 6 7 8 9 10 CSS 1000pF 11 VON VRNG PGOOD MODE_SYNC ITH VFB PLL/LPF 26 SW 25 SENSE+ M1 Si7850DP SENSE 20 BGRTN 19 18 CDRVCC 0.1F M2 Si7850DP 10 D1 B1100 CVCC 1F C5 1F PGND COUT1 270F 6.3V - 21 L1 4.7H VOUT 3.3V 5A BG SHDN SS/TRACK 12 SGND 13 SHDN 14 UVIN SGND CC2 47pF RFB2 3.24k RC 200k DRVCC 17 INTVCC 16 EXTVCC 15 NDRV COUT2 10F 6.3V CC1 5pF RFB1 10.2k 38105 TA04 PACKAGE DESCRIPTION UH Package 32-Lead Plastic QFN (5mm x 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 5.00 0.10 (4 SIDES) 5.50 0.05 4.10 0.05 0.70 0.05 PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP R = 0.115 OR 0.35 x 45 CHAMFER TYP 31 32 0.40 0.10 1 2 3.50 REF (4 SIDES) 3.45 0.05 3.50 REF (4-SIDES) 3.45 0.05 3.45 0.10 3.45 0.10 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC (UH32) QFN 0406 REV D 38105f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC3810-5 TYPICAL APPLICATIO S 13V to 60V Input Voltage to 12V/10A with Trickle Charger Start-Up CIN1 68F 100V VIN 13V to 60V CIN2 1F 100V PGND CON 100pF 1 ION PGOOD RUV1 200k CSS 1000pF SHDN RUV2 13.3k RFB2 1k CC2 47pF RC 200k CC1 5pF RELATED PARTS PART NUMBER (R) DESCRIPTION Synchronous Step-Down DC/DC Controller No RSENSETM Synchronous DC/DC Controller Monolithic 1.5A, 500kHz Step-Down Regulator 50mA, 3V to 80V Linear Regulator Monolithic 3A, 200kHz/500kHz Step-Down Regulator Monolithic Step-Up/Step-Down DC/DC Converter 100V Synchronous DC/DC Controller High Voltage Synchronous Fixed Frequency Step-Down Regulator Controller 100V Current Mode Synchronous Step-Down Regulator Controller High Voltage Synchronous Step-Down Controller with Constant On-Time LT 1074HV/LT1076HV Monolithic 5A/2A Step-Down DC/DC Converters LTC1735 LTC1778 LT1956 LT3010 LT3430/LT3431 LT3433 LTC3703 LT3800 LTC3810 LTC3812-5 LTC3824 LT3844 LT3845 High Voltage Step-Down Controller with 100% Duty Cycle VIN up to 60V, IOUT 7A, Current Mode, Low IQ, 200kHz to 600kHz Fixed Frequency or Synchronizable, MSOP-10 High Voltage Non-Synchronous Programmable Frequency VIN up to 60V, IOUT 10A, Current Mode, Onboard Bias Regulator, Low IQ, TSSOP-16, Synchronizable Step-Down Regulator Controller High Voltage Synchronous Programmable Frequency Step-Down Regulator Controller VIN up to 60V, IOUT 20A, Current Mode, Onboard Bias Regulator, Low IQ, TSSOP-16, Synchronizable 38105f No RSENSE is a registered trademark of Linear Technology Corporation. 36 Linear Technology Corporation (408) 432-1900 FAX: (408) 434-0507 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2007 U RON 263k RNDRV 100k LTC3810-5 28 BOOST TG 27 DB BAS19 CB 0.1F 4 VON 5 VRNG 6 PGOOD 7 MODE_SYNC 8I TH 9V FB 10 PLL/LPF 11 26 SW 25 SENSE+ M1 Si7850DP SENSE - 21 L1 10H BGRTN 20 CDRVCC 0.1F M2 Si7850DP x2 C5 22F PGND COUT1 270F 16V D1 B1100 VOUT 12V 10A SS/TRACK 12 SGND 13 SHDN 14 UVIN SGND 19 BG DRVCC 18 INTVCC 17 EXTVCC 16 15 NDRV 10 COUT2 10F 16V CVCC 1F RFB1 14k 38105 TA05 COMMENTS VIN up to 60V, TO-220 and DD Packages 3.5V VIN 36V, 0.8V VOUT 6V, Current Mode, IOUT 20A 4V VIN 36V, Fast Transient Response, Current Mode, IOUT 20A 5.5V VIN 60V, 2.5mA Supply Current, 16-Pin SSOP 1.275V VOUT 60V, No Protection Diode Required, 8-Lead MSOP 5.5V VIN 60V, 0.1 Saturation Switch, 16-Pin SSOP 4V VIN 60V, 500mA Switch, Automatic Step-Up/Step-Down, VIN up to 100V, 9.3V to 15V Gate Drive Supply VIN up to 60V, IOUT 20A, Current Mode, Onboard Bias Regulator, Low IQ, TSSOP-16 VIN up to 100V, IOUT 20A, Constant On-Time, Synchronizable VIN up to 60V, IOUT 20A, Current Mode, Low IQ, External Bias Regulator Control LT 0507 * PRINTED IN USA |
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